Cam Brown

Senior Logic Design Engineer · Portland, Oregon

Experience

• 

  Ampere Computing

  Senior Logic Design Engineer · April 2026 – present

  Logic Design Engineer · August 2023 – April 2026

  • SoC microarchitect; owner of the CPU's SPR model.
  • Developer and daily user of the in-house SoC integration tools. Work with architecture to settle each product's final floorplan, and provide power, timing, and area data to the SE teams.
  • Design full-stack automated pipelines that parse architectural inputs and generate functionally and physically correct RTL.
  • Grew from fundamental CPU logic design into SoC-wide design automation.
• 

  Ampere Computing

  Logic Design Intern · Summer 2022

  • Wrote new SystemVerilog RTL in the MMU of Ampere's newest custom core.
  • Analyzed the instruction decoder with the team to reduce logical effort, saving up to 1.5% CPU power.
  • Identified power-intensive events in ULMs across the core and built a pre-synthesis tracker for them.
• 

  SAS Institute

  Technical Intern, Machine Learning · June 2020 – August 2021

  • Engineered automated test specifications in Groovy, including the primary smoke test for VDMML that runs on every push through the promotion pipeline.
  • Automated bug triage for several SAS Viya teams with a suite of Python tools that resolved server-side performance issues.
  • Worked daily with Docker, Jenkins, Kubernetes, and the rest of the CI/CD stack.

Education

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  Northwestern University

  MS, Computer Engineering · June 2023

  BS, Computer Engineering · June 2022

  • McCormick School of Engineering and Applied Science. MS concentration in architecture and VLSI algorithmics; GPA 3.9.
  • IEEE member. Club baseball.
• 

  Carleton College

  Computer Science and Mathematics · 2018 – 2020

  • Recruited out of high school to varsity baseball, NCAA Division III.

Skills